A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A typical vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word line plates, control gate plates) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming a so-called “stair step” structure at edges (e.g., lateral ends) of the tiers of conductive structures. The stair step structure includes individual “steps” defining contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures.
Conventional processes for forming a stair step structure generally include repeated acts of trimming a photoresist overlying alternating conductive structures and insulating structures, etching portions of the insulating structures not covered by a remaining portion of the photoresist, and then etching portions of the conductive structures not covered by remaining portions of the insulating structures. Such conventional processes typically result in the formation of so-called “stadium” structures exhibiting opposing and symmetric stair step structures. A first stair step structure on a first end of a stadium structure typically mirrors a second stair step structure on a second end of the stadium structure. The first stair step structure and the second stair step structure generally exhibit substantially the same size and substantially the same shape, but the first stair step structure outwardly extends in a direction that opposes a direction in which the second stair step structure outwardly extends. For various applications, however, only one stair step structure (e.g., only the first stair step structure or only the second stair step structure) of the stadium structure is used to make electrical connections, and the other stair step structure (e.g., the second stair step structure or the first stair step structure) of the stadium structure is underutilized and/or occupies space that could otherwise be utilized for another, more desirable purpose.
It would, therefore, be desirable to have improved methods of forming stair step structures for semiconductor devices (e.g., vertical memory devices, such as 3D NAND Flash memory devices) that reduce, if not eliminate, the aforementioned problems.